FIELD OF THE INVENTION
The invention relates to an integrated semiconductor circuit disposed in at least one semiconductor body and having the following features:
a) at least one terminal pad, which is connected via an electrically conductive connecting line to the integrated semiconductor circuit; PA1 b) at least one first busbar, which carries a first supply potential of the integrated semiconductor circuit during operation; PA1 c) at least one second busbar, which carries a second supply potential of the integrated semiconductor circuit during operation; PA1 d) at least one protective element for protecting the integrated semiconductor circuit against electrostatic discharge, the protective element being arranged between the terminal pad and the integrated semiconductor circuit and being connected to at least one of the busbars; PA1 e) the protective element having at least one integrated vertical protective transistor, having at least one base zone, at least one emitter zone and at least one collector zone, whose load path is connected between the connecting line and one of the busbars and whose base terminal can be driven by a driving means. PA1 a semiconductor body and an integrated semiconductor circuit disposed in the semiconductor body; PA1 a terminal pad and a connecting line electrically connecting the terminal pad to the integrated semiconductor circuit; PA1 a first busbar carrying a first supply potential during an operation of the integrated semiconductor circuit; PA1 a second busbar carrying a second supply potential during an operation of the integrated semiconductor circuit; and PA1 a protective element for protecting the integrated semiconductor circuit against electrostatic discharge connected between the terminal pad and the integrated semiconductor circuit and to at least one of the first and second busbars; PA1 the protective element including at least one integrated vertical protective transistor having a load path connected between the connecting line and one of the first and second busbars and having a base and a collector disposed laterally offset with respect to one another.
A so-called ESD protective element of this type is disclosed in J. Chen, X. Zhang, A. Amerasekera and T. Vrostos; Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits, Proc. of the IEEE International Reliability Physics Symposium (1996), p. 227.
Semiconductor circuits integrated in a chip contain protective circuits for protecting the inputs or outputs (I/O ports) against electrostatic overvoltages and electrostatic discharges (ESD) caused thereby. These so-called ESD protective elements are connected between the input pad of an integrated semiconductor circuit and the input or output terminal to be protected, and consequently ensure that when a parasitic overvoltage is coupled in, the ESD protective element is turned on and the parasitic overvoltage pulse is consequently conducted away to one of the supply voltage conductor tracks. Such overvoltage pulses can lead, in the extreme case, to the destruction of the component.
Under operating conditions as are described for example in the product specification, however, the ESD protective elements must not adversely affect the function of the integrated semiconductor circuits to be protected. This means that the turn-on voltage of the ESD protective elements must lie outside the signal voltage range of the protected terminal pads. In order to be able to develop a good protective action, the ESD protective element should break down before the critical circuit path. As a rule, this requires an exact setting of the turn-on voltage of the respective ESD protective elements with the essential boundary condition that the process control, which has been optimized with regard to the properties of the components of the integrated semiconductor circuit to be protected, is not altered by the insertion of the ESD protective elements.
A further essential boundary condition results from the spatial arrangement of the terminal pads in immediate proximity to the integrated semiconductor circuit to be protected. In particular, the terminal pads are arranged in the vicinity of the output drivers owing to the relatively high current to be driven. The ESD protective structure is therefore frequently connected to that supply line from which the output driver is supplied.
For terminals that may be exposed to very fast voltage edges without the external circuitry ensuring sufficient current limiting, particular care must be taken, given the use of ESD protective elements which have a so-called snap-back behavior in the event of breakdown, to ensure that the withstand voltage lies above the specified signal voltage in order thereby to avoid a transient turn-on (latch-up effect) of the ESD protective elements. This latch-up effect of the ESD protective elements frequently leads to their destruction and, consequently, also to the destruction of the integrated semiconductor circuit connected downstream.
For these reasons, protective transistors, in particular npn bipolar transistors, or thyristors having a withstand voltage in the signal voltage range cannot be used as ESD protective elements, despite the high ESD strength and the good protective action. This applies particularly to semiconductor circuits fabricated using smart power technology. One is restricted here to breakdown diodes or transistors having a low gain, which have a low ESD strength in comparison with the components described above.
The withstand voltage of npn bipolar transistors, in particular of actively driven npn bipolar transistors, is described by the relationship EQU U.sub.H =U.sub.CB *.beta..sup.-1/4
where .beta. is the collector-base current gain and U.sub.CB is the collector-base breakdown voltage.
In order to increase the withstand voltage of the bipolar transistors, according to the equation above it is necessary either to increase the collector-base breakdown voltage or to reduce the current gain. However, a reduction of the current gain is not advantageous since the protective action would also be impaired as a result.
Consequently, it is necessary to increase the collector-base breakdown voltage in order to increase the withstand voltage of the protective element. At the same time, however, the breakdown voltages of the remaining components of the integrated semiconductor circuit must not be altered. From the boundary conditions described above, then, an enlargement of the epitaxial layer thickness and/or a reduction of the doping in the epitaxial layer are ruled out.
With regard to further details, features, their advantages and method of operation of the ESD protective circuits, reference is expressly made to European Patent Application EP 0 623 958 A1 and also to the document by J. Chen et al. mentioned in the introduction. These are incorporated by reference in their entirety.